New Contributor
Super ContributorHi
Apologize for the long delay as I’m OOO for that week. The issue you are encountering with the System ID and timestamp mismatch, along with the Open Core Plus Status popup, is related to the use of licensed IP cores in the Quartus Prime Lite Edition.
· This error occurs when the System ID and timestamp embedded in the software project do not match those in the FPGA hardware design. This typically happens if the hardware design was modified and not recompiled, or if the software project was not updated with the new hardware system information.
· This popup indicates that you are using IP cores in evaluation mode (Open Core Plus mode), which allows you to use the IP core for a limited time for evaluation purposes. The message "Time remaining: unlimited" means that the IP core is in evaluation mode, but the timer has not started.
Some suggestion to the issue.
Recompile the Hardware Design:
Ensure that you have recompiled the Quartus project after any changes to the Qsys (Platform Designer) system.
Open your Quartus project and compile it to generate the latest System ID and timestamp.
Update the Software Project:
After recompiling the hardware design, update your software project in the Eclipse IDE to reflect the new System ID and timestamp.
In Eclipse, go to Nios II -> Run Configuration -> Target Connection tab.
Click on Refresh Connections to detect the new System ID and timestamp.
Check for Licenses:
If your design uses licensed IP cores, you will need to obtain the appropriate licenses. The Lite Edition of Quartus Prime does not support some licensed IP cores.
You can check the IP cores used in your design and see if any of them require licenses that are not available in the Lite Edition.
Request No-Cost Licenses:
For some IP cores, you might be able to obtain no-cost licenses for evaluation or academic purposes. Visit the Self-Service Licensing Center https://licensing.intel.com/psg/s/ to explore options for no-cost or evaluation licenses.
For academic, Sign into the FPGA Academic Program website and request software licenses and hardware from there.
https://www.intel.com/content/www/us/en/developer/topic-technology/fpga-academic/membership.html
New ContributorAfter following your suggestions I still found the same results.
1. I created the qsys design.
2. I generated the HDL, which created the qsys and sopc files
3. I compiled the entire design in Quartus and programmed it into the MAX 10 FPGA.
4. The pop-up with "Time remaining: unlimited" appeared.
5. I created a new template in Eclipse using the generated qsys and sopcinfo files.
6. After a successful build I went to Nios II -> Run Configuration -> Target Connection tab.
7. I Refreshed Connections to detect the new System ID and timestamp and System ID and timestamps did not match.
Could it be because the message "Time remaining: unlimited" pops-up or is this a separate issue?
Also, how would I know which IP cores need licenses?
Thanks for the help!
