Hey,I am using MegaFunction to instantiate M9K SRAM blocks in my design and the Quartus 17.0 software always syntheszies away my M9K blocks, my design consists of Reset signal and the memory blocks driving outputsPlease help this issue is driving me crazyMy board is DE2-115

Well, if Quartus detects that your memory is never written and holds a constant data pattern it can optimize it away and replace it with simple logic.Quartus is pretty smart about optimizing away logic it detects as not being used (eg, generated logic that does not drive any other logic can be eliminated).

Quartus will show the reason why those ram was optimized away. Can you check in your Processing -> Compilation report. Look into all the details over there.

What I did is building a module that generates Sine wave and save enough samples of this wave in M9K blocks then I connect M9K blocks to VGA driver block so that I can see output on the screen but the fitter keeps destroying the entire memory and I don't know why

First, does the design run in simulation? You describe what the design is supposed to do, but does it behave that way in simulation?Second, look in your design .map.rpt file, couple of sections: 16. Registers Removed During Synthesis 17. Removed Registers Triggering Further Register Optimizationswill tell you which register blocks have been removed, and give a reason why.

The design runs in simulation as expected and to make sure more I made a hardware test where I used the VGA chip as a DAC and saw the sine on my scope and everything works perfectly but the problem arises after connecting the M9K blocks to internalcircuity to move on on my projectI will check the rest now

My M9K blocks get always synthesized away!

14 Replies

KennyT_altera
Super Contributor
6 years ago
Did you check on the technology map viewer as well? If it is synthesized away, those logic will be gone there.
AAlas3
Occasional Contributor
6 years ago
Yes, all of them are gone in Technology Map Viewer, Quartus destroyed a great portion of the system
ak6dn
Regular Contributor
6 years ago
GND and logic low behave identically. So do VCC and logic high.
Quartus did not destroy anything. It optimized out logic that could be replaced by a constant value. You most likely need to check your design.
There is an outside chance you have found a bug in Quartus, but you are going to need substantial proof to claim this is true.
AAlas3
Occasional Contributor
6 years ago
it appears that the problem was due to incomplete Verilog description, I just added a couple of "If statements" and everything worked fine

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My M9K blocks get always synthesized away!

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