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Altera_Forum
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12 years ago

My clock port cannot be matched as a port

I need information about the critical path in my circuit. I first tried to use Quartus II 9.1 with classical timing analyzer but I obtained

the warning message "No paths found for timing analysis". Now I'm trying with the new version Quartus II 12.1 sp1.

This is my top entity vhdl code 


library ieee;
use ieee.std_logic_1164.all;
use work.my_types.all;
entity qc_enc is
    generic(    N: positive := 20;
                K: positive := 10;
                L: positive := 5);
    port(
        CLOCK_50:    IN std_logic;
        KEY:            IN std_logic_vector(0 downto 0); -- reset_n
        GPIO_0:        IN std_logic_vector(K-1 downto 0); -- u
        GPIO_1:        OUT std_logic_vector(2*L-1 downto 0));--p_ij 
end qc_enc;

This is the mapping on the Pin Planner window:

https://www.alteraforum.com/forum/attachment.php?attachmentid=6863

I've tried to create a clock in TimeQuest Timing Analyzer with the command 

create_clock -name clock -period 20.000

receiving the following errors: 


  Ignored filter: CLOCK_50 could not be matched with a port
Ignored create_clock: Argument <targets> is an empty collection

In fact it is not present in the list of all ports:

https://www.alteraforum.com/forum/attachment.php?attachmentid=6862

Furthermore I have not any port called LVDS150p/nCEO.

Thanks in advance for your help.

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