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Altera_Forum's avatar
Altera_Forum
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13 years ago

My clock port cannot be matched as a port

I need information about the critical path in my circuit. I first tried to use Quartus II 9.1 with classical timing analyzer but I obtained the warning message "No paths found for timing analysis...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Is CLK_50 connected in your design to an actual function? You may check the RTL netlist.

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Furthermore I have not any port called LVDS150p/nCEO

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nCEO is an optional dedicated pin, I guess you have enabled it in the device settings.