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Altera_Forum's avatar
Altera_Forum
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15 years ago

MUX SEL input "was determined to be a clock"?!?

Hi,

I have been very happy that I'm finally able to constrain my design in Timequest.

However, I added one mux in my .bdf (see attachment) to let the Nios decide which of my components can send it's data via the UART TX line. The Sel input of the mux is connected to a GPO of my Nios system. Now, after compilation is finished, I get the message that this signal at the sel input "... was determined to be a clock but was found without an associated clock assignment".

How can that be and what can I do against it?

Thanks,

Maik

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    That generally means it's driving a clock port of a register. Obviously from the description that sounds incorrect. A few thoughts:

    - Look in the Fitter Report -> Resource Section -> Control Signals, sort on Usage and look at everything that is a Clock. This is not a TimeQuest report, but a physical report of everything that drives the .clk pin of a register. Just see if something stands out.

    - In TQ, put a create_clock assignment on the signal it says, then do report_timing to that clock. See what shows up.
  • Altera_Forum's avatar
    Altera_Forum
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    Hi Rysc,

    the signal is not listed in the Fitter report as a clock.

    I must apologize for writing the wrong signal that was reportet as a clock. It's not that one that drives the MUX Sel port. It is a signal of a 8 bit wide data bus that is transferring a received uart word from one component to an other.

    However, I followed this signal through the RTL viewer but it does not end at a clock input. It just goes from one output register to an input register as data line (from Q to D). The clocks of those register are well defined clock signals.

    When I put a clock assignment on this signal, then everything seems to be okay for TQ. But not for me . . .

    Is there a way to let TQ or the Fitter or whoever tell me on what clock input this signal is (in it's opinion) connected?

    Thanks,

    Maik
  • Altera_Forum's avatar
    Altera_Forum
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    report_timing -setup -npaths 10 -detail full_path -from_clock $clock_name -panle_name "from clock"

    report_timing -setup -npaths 10 -detail full_path -to_clock $clock_name -panle_name "to clock"

    replace $clock_name with the name of the clock you've created.
  • Altera_Forum's avatar
    Altera_Forum
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    Hi Rysc,

    thats what is listed in the timing report, now:

    From Node:

    ad_tpdb_qsys:inst2|uart:uart_0|uart_rxtx:b2v_inst|tx_data[8]

    To Node:

    uart_tx_mux:inst20|lpm_mux:LPM_MUX_component|mux_96e:auto_generated|result_node[0]~1

    Launch Clock:

    inst|altpll_component|auto_generated|pll1|clk[1]

    Latch Clock:

    test_clk

    In the attachment, you can see the RTL of the From Node and To Node.

    I have no idea why it is thinking that this signal is a clock . . .

    Maik
  • Altera_Forum's avatar
    Altera_Forum
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    Do me a favor and add -file "TQ_setup.txt" and -file "TQ_hold.txt" to the report_timing commands, then attach the reports. Looks strange.

    (I am out and busy with some other stuff, so you might want to file an SR and then post the results here...)