MUX SEL input "was determined to be a clock"?!?

Hi Rysc,

thats what is listed in the timing report, now:

From Node:

ad_tpdb_qsys:inst2|uart:uart_0|uart_rxtx:b2v_inst|tx_data[8]

To Node:

uart_tx_mux:inst20|lpm_mux:LPM_MUX_component|mux_96e:auto_generated|result_node[0]~1

Launch Clock:

inst|altpll_component|auto_generated|pll1|clk[1]

Latch Clock:

test_clk

In the attachment, you can see the RTL of the From Node and To Node.

I have no idea why it is thinking that this signal is a clock . . .

Maik