Multiply-by-2 clock

How is the internal clock frequency generated?

Do you have an external circuit that generates both the 125 MH base_clock and the 250 MHz clock?

Hello rbugalho and Rysc,

Yes as you said, I have two physical ports to the module: base_clock and clock. I have attached the verilog modules in this post. PMP_2w4r is the main module. It instantiates a bank of block RAMs, a multipumping controller, some delays and muxes, and makes it all appear as a single memory with 2 write ports and 4 read ports that externally operates on the system clock, but internally operates at double that clock speed.

As the altera documentation says, the base clocks are generated externally and multiplied clocks are generated by on chip PLL s. That is why I gave such a clock constraint in the .sdc file.

@Rysc - The answer to your question "So you have two physical ports on your design, one called base_clock and the other called clock? How does the first input connect up to the second one?" . Hmmm, the clock = 2 * base_clock. There is no other connection between them. The verilog module "multipumping controller" generates phase signals alongside the multiplied clock to force the internal operations of the memory controlled by the multiplied clock to occur with a certain phase relationship relative to the external operations controlled by the system clock.

Hope this helps.

That really doesn't answer the question.

Anyway, the issue is the following:

"create_clock" is used to describe base clocks which are provided as FPGA input signals. It is also used to describe virtual clocks, which are not used in the FPGA.

"create_generated_clocks" is used to describe clocks which are generated inside the FPGA from other clocks, either via a FPGA PLL or via a clock dividing logic.

If PMP_2w4r is the main module, then you are providing both clock and base_clock to the FPGA as base_clocks from the external FPGA. You need to constrain them both using create_clock.

It still begs the question of how they are generated.

If they are externally derived from the same reference, then you can leave them as related clocks and let the tool analyse the timings. You should add some clock uncertainty/latency though, to account for external skews between them.

If they are not externally derived from the same reference, then you must treat them as unrelated clocks, use asynchronous clock domain crossing techniques in your design and also cut the timing analysis between those two clocks, using set_clock_groups or set_false_path.

Thanks for the help rbugalho. I used create_clock constraint to generate both the clocks.

However, one strange thing that I noticed is that the tool is reporting the Fmax of the external clock as approximately twice that of internal clock! It should have been the other way round.

In the .sdc file my base_clock = 8ns => 125 MHz, internal_clock = 4ns => 250 MHz. But the Fmax for the base_clock = 625 MHz and Fmax for internal_clock = 303 MHz. Even though the multiplied by 2 factor is still maintained between the 2 clocks, I am not able to understand why the relationship is flipped!

Is it because of the fact that since the internal_clock is not generated by the base_clock and since they are independent of each other Quartus calculates the Fmax for each clock separately?