Multiply-by-2 clock

Hello rbugalho and Rysc,

Yes as you said, I have two physical ports to the module: base_clock and clock. I have attached the verilog modules in this post. PMP_2w4r is the main module. It instantiates a bank of block RAMs, a multipumping controller, some delays and muxes, and makes it all appear as a single memory with 2 write ports and 4 read ports that externally operates on the system clock, but internally operates at double that clock speed.

As the altera documentation says, the base clocks are generated externally and multiplied clocks are generated by on chip PLL s. That is why I gave such a clock constraint in the .sdc file.

@Rysc - The answer to your question "So you have two physical ports on your design, one called base_clock and the other called clock? How does the first input connect up to the second one?" . Hmmm, the clock = 2 * base_clock. There is no other connection between them. The verilog module "multipumping controller" generates phase signals alongside the multiplied clock to force the internal operations of the memory controlled by the multiplied clock to occur with a certain phase relationship relative to the external operations controlled by the system clock.

Hope this helps.