Multiply-by-2 clock

That really doesn't answer the question.

Anyway, the issue is the following:

"create_clock" is used to describe base clocks which are provided as FPGA input signals. It is also used to describe virtual clocks, which are not used in the FPGA.

"create_generated_clocks" is used to describe clocks which are generated inside the FPGA from other clocks, either via a FPGA PLL or via a clock dividing logic.

If PMP_2w4r is the main module, then you are providing both clock and base_clock to the FPGA as base_clocks from the external FPGA. You need to constrain them both using create_clock.

It still begs the question of how they are generated.

If they are externally derived from the same reference, then you can leave them as related clocks and let the tool analyse the timings. You should add some clock uncertainty/latency though, to account for external skews between them.

If they are not externally derived from the same reference, then you must treat them as unrelated clocks, use asynchronous clock domain crossing techniques in your design and also cut the timing analysis between those two clocks, using set_clock_groups or set_false_path.