Contributor
Regular ContributorHi,
The design failed synthesis stage with error below:
Error (13076): The node "VGAController:vgaController|dataH" has multiple drivers due to the conflicting nodes "dataBus[*]" and "SDRAMController8Bit:sdramController|ioData[*]"
In the design dataH is connected to
dataH >iData (vgaController) > dataBus
In SystemVerilogTest1.sv, dataBus receives input from ioData and dataOut. Here is where the conflict is. I tried to comment out Line142 and the compilation is successful.
Line 142: assign dataBus = ( chipSelectRAM ) ? dataOut : 16'bZZZZZZZZZZZZZZZZ;
Line 180: .ioData( dataBus ),
Thanks
Best regards,
KhaiY
ContributorHi @KhaiChein_Y_Intel . Thank you for looking into this. I still do not understand how dataH becomes connected to iData.
VGAController.sv only has the below line:
dataH = iDataCopy[ 15 : 8 ];
My understanding will be wrong, but I am thinking that dataH is driven by the iDataCopy registers. iDataCopy is fed by the dataIncoming registers. This would mean that iData and dataH are seperated by 2 registers:
dataH <-- iDataCopy <-- dataIncoming <-- iData (dataBus/ioData)
Can you please explain to me how iData is a multiple driver of dataH? If iData was connected directly to dataH, I could understand this.
Sorry, but there is something small and fundamental here that I am not seeing/understanding.
Contributor@KhaiChein_Y_Intel I have looked at the RTL Viewer (something I tend to avoid) and I can see why the compiler error has been created. However.. the iDataCopy and dataIncoming registers are missing!
According to my VGAController.sv file, there should be a chain of components like this:
a) dataH <-- iDataCopy <-- dataIncoming <-- iData
But what I see inside the RTL Viewer is this:
b) dataH <-- iData
Where did iDataCopy and dataIncoming go??
Has the compiler has optimized my design in such a way that it no longer works?? How can I ensure that my chain is synthesized as I expected it to be in (a) above?
