multiple constant drivers for net IOP_

Hi,

Your "inputpin" is driven twice once in the comb. statement and once in the instantiation of IOP. Buffer means output, you better avoid this type of port. Your signal names are very confusing.

IOP_ALU consists of 2 module: IOP and ALU(DUT). the inputpin mentioned(confused) is the input to DUT which is the output of the IOP as you can view in the attachment. Actually i study on somebody code and i cant answer you about the use of buffer.

At the same time i would like to ask that is the mode buffer in verilog as well? If yes what is the function.

As you comment before, there are combination statement and instantiation statement. On the other hand, it is working when i compile the module IOP. It also contain the combination statement and instantiation statement. The code of IOP is as bellow:

-- final_lo

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

entity IOP is

generic (

n: integer := 28;

m: integer := 8

);

port (

-- testing_cout_out : out std_logic_vector(7 downto 0);

reset_b : in STD_LOGIC;

serial_out : out std_logic;

serial_in : in std_logic;

-- error1 : out std_logic;

-- error2 : out std_logic;

clk_25mhz : in STD_LOGIC;

-- input_eq : out std_logic;

-- t_out_equal : out std_logic;

inputpin : buffer std_logic_vector(m-1 downto 0);

outputpin : in std_logic_vector(n-1 downto 0);

ack : out std_logic ;-- signal from to indicate continue CPU execution

busy : in std_logic -- signal to indicate transfer data

);

end IOP;

architecture IOP_arch of IOP is

signal clk_1mhz_int : std_logic;

signal sig_idle,ready_in :std_logic;

signal t_out_eq,eq_zero : std_logic;

signal data_selected : std_logic_vector(7 downto 0);

signal data_fsm : std_logic_vector(7 downto 0);

signal control : std_logic_vector(16 downto 0);

signal get_data,fsm_data_load,t_input_load,t_output_load,i_load,i_inc,i_clr,o_load,o_inc,o_clr,transfer : std_logic;

signal data_selected_load : std_logic;

signal trans,recv : std_logic;

signal load_command : std_logic;

signal data_selected_reg : std_logic_vector(7 downto 0);

signal end_data : std_logic_vector(1 downto 0);

signal data_out : std_logic_vector(8 downto 0);

signal command : std_logic_vector(7 downto 0);

-- VHDL Module Generator component declarations

component clk_1mhz

port (

reset : in STD_LOGIC;

clk_25mhz : in STD_LOGIC;

clk_1mhz : out STD_LOGIC

);

end component;

component IOP_CU

port (

reset : in STD_LOGIC;

clk_1mhz : in STD_LOGIC;

sig_idle : in STD_LOGIC;

ready_in : in STD_LOGIC;

t_out_eq : in STD_LOGIC;

eq_zero : in STD_LOGIC;

data_selected : in STD_LOGIC_VECTOR(7 downto 0);

data_fsm : in std_logic_vector(7 downto 0);

control : out STD_LOGIC_VECTOR(16 downto 0);

command : in std_logic_vector(7 downto 0);

ack : out std_logic ;-- signal from io processor to indicate continue execution

busy : in std_logic -- signal to io processor to indicate interrupt to transfer data

);

end component;

component IOP_DPU

generic (

n: integer := 12;

m: integer := 12

);

port (

-- testing_cout_out : out std_logic_vector(7 downto 0);

transfer : in std_logic;

get_data : in std_logic;

reset_b : in std_logic;

clk25mhz : in STD_LOGIC;

clk_1mhz : in std_logic;

serial_out : out std_logic;

sig_idle : out std_logic;

serial_in : in std_logic;

-- error1 : out std_logic;

-- error2 : out std_logic;

ready_in : out std_logic;

i_load : in std_logic;

i_inc : in std_logic;

i_clr : in std_logic;

-- input_eq : out std_logic;

o_load : in STD_LOGIC;

end_data : in std_logic_vector(1 downto 0);

o_inc : in STD_LOGIC;

o_clr : in STD_LOGIC;

t_out_eq : out STD_LOGIC;

eq_zero : out std_logic;

data_selected_reg : buffer std_logic_vector(7 downto 0);

data_fsm : out std_logic_vector(7 downto 0);

t_input_load : in STD_LOGIC;

t_output_load : in std_logic;

fsm_data_load : in std_logic;

data_selected_load : in std_logic;

trans : in std_logic;

recv : in std_logic;

inputpin : buffer std_logic_vector(m-1 downto 0);

outputpin : in std_logic_vector(n-1 downto 0);

load_command : in std_logic;

command : buffer std_logic_vector(7 downto 0)

);

end component;

begin

-- VHDL Module Generator component instantiations

load_command<=control(16);

get_data<=control(15);

fsm_data_load<=control(14);

data_selected_load<=control(13);

t_input_load<=control(12);

t_output_load<=control(11);

i_load<=control(10);

i_inc<=control(9);

i_clr<=control(8);

recv<=control(7);

trans<=control(6);

o_load<=control(5);

o_inc<=control(4);

o_clr<=control(3);

end_data(1)<=control(2);

end_data(0)<=control(1);

transfer<=control(0);

u_clk_1mhz: clk_1mhz

port map (reset_b, clk_25mhz, clk_1mhz_int);

u_iop_cu: iop_cu

port map (reset_b, clk_1mhz_int, sig_idle, ready_in, t_out_eq, eq_zero, data_selected, data_fsm, control,command,ack,busy);

u_iop_dpu: iop_dpu

generic map (n,m)

port map (transfer, get_data, reset_b, clk_25mhz, clk_1mhz_int, serial_out, sig_idle, serial_in, ready_in, i_load, i_inc, i_clr, o_load,end_data(1 downto 0),o_inc,o_clr,t_out_eq, eq_zero, data_selected, data_fsm, t_input_load, t_output_load, fsm_data_load,data_selected_load,trans,recv,inputpin,outputpin,load_command,command);

end IOP_arch;

Howerver there are errors in top level IOP_ALU. Can you explain on it. Thanks

Hi,

There are two issues that I raised. One is your error of double drive, the second is a recommendation about buffer port.

Your error will appear when you connect IOP & ALU as one project. You are driving inputpin from two sources:

Drive 1: inputpin <= selop & R0 & A & B;

Drive 2: inputpin is driven by IOP module

I am not saying don't mix comb. with other statements but you can't drive from more than one source in VHDL. If you need more than one drive then you must write a correct construct to resolve the drive.

As to buffer port: This is almost obsolete type of vhdl port(not verilog). It is meant for outputs that need to be read inside module instead of intermediary signal. You better avoid it and use intermediary signal if you want to read your output. Verilog has "buf" which is not a port but actual buffer function.

I aggree, that buffer can and should be avoided. The problem however isn't due to the buffer port type rather than the fact, that's an output (as any buffer).

To add my strongest personal dislikings in the present post: Positional association with component instantiation. And - unneccessary long example code, that could be easily reduced, which would be also the first step to locate the coding error by yourself.

Thanks for the advice.

Why there is error in version 7.1 and no error in version 8.0? Just wonder..

How to

What is the meaning of “ ”?

for example :

generic (

Note: note := "Receiver shift register"

);

Regarding the second question, it's a VHDL string constant. Cause VHDL strings aren't directly synthesizable (at best, they may be casted to a synthesizable type in some cases), they are mainly used as generics with parameterizable components and in simulation.

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Why there is error in version 7.1 and no error in version 8.0? Just wonder..

--- Quote End ---

Cause I wasn't able to validate the error from the presented code, I can just guess. It may be the case, that the said buffer port isn't driven in the component (so, it isn't actually an output) and that the Quartus behaviour was changed in this respect. I remember some oddities with inconsistent defined buffer ports with previous Quartus versions. The issue can be verified only by interrogating the component code.