Multiple constant driver error

[h=1]This is the verilog code i have written in quartus 2 .... Bt after compilation i m getting "Can't resolve multiple constant drivers for net" such errors.... i guess it is something related to the always block... how should i correct those errors... i m new to quartus2 ... plz let me know if there is any solution to this..

module switch_model( s0,s1,s2,s3,rst,clk);

input rst,clk;

output reg s0,s1,s2,s3;

reg [15:0] counter;

// reg clk_50;

initial

begin

s0=1'b0;

s1=1'b0;

s2=1'b0;

s3=1'b0;

end

genvar i;

generate

for (i=0;i<255;i=i+1)

begin

always @(posedge clk)

begin

s0<=1'b1;

s1<=1'b1;

# 50 s2<=1'b1;

s3<=1'b1;

end

end

endgenerate

endmodule[/h]