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Altera_Forum's avatar
Altera_Forum
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16 years ago

Multiple clock assignment to SOPC module

Hi, I have made an SOPC module with the "New component..." vizard. The VHDL code for the component contains one Avalon MM interface, one Avalon ST interface, and some signals that are exported ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hello,

Maybe you can use the RTL VIEWER.

This way you can see how was synthetyzed your hardware.

Regards,

Diego