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L982123's avatar
L982123
Icon for New Contributor rankNew Contributor
6 years ago

Multi-phase data recovery design constraints

Hi, I have a design where an input is being oversampled by using multiple phase outputs from a PLL. To make this work I need to ensure that the skew between the input and each sampling register is...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,


Does the skew value in the report_skew report less than the value you set using set_max_skew? Can you check if this constraint is being ignored and listed in the Ignored Constraints report? Have you tried setting the clock to global signal?

Thanks

Best regards,

KhaiY