Modified default value of generic parameter does not trigger correct make on Q17 ?

Hello,

The following module intializes the parameter of ent_bug 'v' with value 1 and the second one instantiates the first module and sends the output to a 7SEG display of a DE0:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent_bug is
  generic(v : integer := 1);
  port(result : out std_logic_vector(3 downto 0));
end ent_bug;
architecture arch_bug of ent_bug is
begin
   result <= std_logic_vector(to_unsigned(v,4));
end;

and

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent_main is
  port(
  CLOCK_50  : in std_logic;
  HEX5 : out std_logic_vector(6 downto 0)
 );
end ent_main;
architecture arch_main of ent_main is
 signal bugVal : std_logic_vector(3 downto 0);
 begin
   ENTB: entity work.ent_bug(arch_bug) port map(result=>bugVal);
   SEG5: entity  work.ent_led7seg(arch_led7seg) port map(data=>bugVal,leds=>HEX5);
 end arch_main;

The code above results in '1' on the7seg of my DE0 correctly.

However if i Change and save:

generic(v : integer := 5);

=> I keep getting '1' on my DE0 7 Seg display.

And if I delete the Db and Incremental_db directory of my project and recompile,

I get '5' on the display (= correct) ??

I have the impression that quartus 17.0 is not recompiling/linking my modified file and sticks to the result of the previous compile of the file.

Is there someting I did oversee (settings ?) or is this something Quartus is not supposed to do ?

(both files are included in the project in the order presented above, the result was reproduced in multiple instances)

Best Regards,

Johi.