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Yes, this will likely be signals inside the design being uninitialised, and fairly normal. So normal and annoying, there is an option to turn warnings like these from numeric_std off.
Simulation -> runtime options -> "suppress warnings" from Synopsys Packages (from std_logic_unsigned/arith) From IEEE packages (numeric_std)
If you're running from a script, set these variables before the run command:
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
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Thanks for the help. It was not the warnings that bothered me but that I assumed they were stopping my waveform from generating. Actually it was something unrelated - in the code I pasted, there is a possibility for no time to run at all, as there's no wait statement. Moving onto the next state was dependent on x cycles occurring, so this broke the entire simulation and I assumed it was the warnings. Fixed now - thanks for telling me about the warnings commands.
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