Forum Discussion
Altera_Forum
Honored Contributor
8 years agoYes, this will likely be signals inside the design being uninitialised, and fairly normal. So normal and annoying, there is an option to turn warnings like these from numeric_std off.
Simulation -> runtime options -> "suppress warnings" from Synopsys Packages (from std_logic_unsigned/arith) From IEEE packages (numeric_std) If you're running from a script, set these variables before the run command:
set StdArithNoWarnings 1
set NumericStdNoWarnings 1