Honored ContributorHello to all,
I noticed that Modelsim compiling time is very lower than Quartus. During initial stage of projects (simulation) this can be very time-saving. There are settings in Quartus to make it fast as ModelSim? (Analysis & Synthesis only) I noticed also that Q14.1 is slower than Q13.1 Thank you
Honored ContributorModelsim compiling is different than Quartus. Modelsim is figuring out the logic and making a simulation model. Quartus is making logic(LUTs, FFs, etc.).
Honored ContributorThere isn't a way to do only syntax check with Quartus?
Honored ContributorIf you have an HDL file open in Quartus, you can do Processing -> Analyze Current File, which is the fastest. For the whole project, do Processing -> Start -> Hierarchy Elaboration for a quick pass through. It won't catch all logical errors, but things like syntax will be caught.
Honored ContributorOk, thank you very much
Honored ContributorAnalysis and elaboration will catch the same syntax errors that modelsim would find.
One of the biggest annoyances for long compilation problems is component mappings in VHDL. Using direct instantiation instead of components and mapping to an entity means the compiler will check the entity rather than the component, so the compiler can figure out the problem rather than the mapping/synthesis.
