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Altera_Forum's avatar
Altera_Forum
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14 years ago

Modelsim simulation in Linux

Hi,

I've been using Quartus II for a school work, but there we were taught how to simulate using Vector Waveform inside Quartus II in version 9.01 . I'm having a little trouble trying to do that with Modelsim.

I'm following the tutorial found in altera . com/literature/ug/ug_gs_msa_qii.pdf , but when I try to add a clock, for example, no waveform appears. It appears for constant '1' or '0' signals, but still don't simulate and sometimes the program crashes.

Can someone helpe figure this out, or tell me where I can get the 9.01 version with which I can simulate using the old method? I don't have much time to spend learning this tools, so that's why I'm asking for your help.

Thanks in advance,

Luiz.

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi Luiz,

    What language are you using? VHDL or Verilog?

    I'll post a simple testbench example to get you started.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi Dave,

    I'm using VHDL. The clock problem I figured out. It was because I wasn't setting an initial value for it, but now the waveforms appears properly. Still, it doesn't simulate. I set the waveforms for all the inputs, click on simulate, but it doesn't happen anything. When I try again, Modelsim closes.

    I would appreciate if you could post the testbench for me.

    Thank you very much,

    Luiz.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    I'm using VHDL ... I would appreciate if you could post the testbench for me.

    --- Quote End ---

    Here's an example component, testbench, and simulation script. There's a readme.txt file in the zip file that I'll repeat here: 

    
Modelsim Example
----------------
10/24/2011 D. W. Hawkins (dwh@ovro.caltech.edu)
This design shows an example of a simple Modelsim simulation
for a VHDL design. The design consists of a register with a
veriable width. The register can be enabled to store the
data on its input, or the inverse of the data on its input.
The testbench performs a walking 1's test for each of the
input modes, and checks the output is consistent with the
input.
To run the test, start Modelsim, change to the top-level
folder of this project and run the sim.tcl script, eg.,
under Windows
ModelSim> cd {C:\temp\modelsim_example}
ModelSim> source scripts/sim.tcl
and then run the testbench
ModelSim> example_tb 16
which will generate the output:
#  ==============================================================================#  Example testbench#  ==============================================================================#         210 ns:  Synchronously deassert reset#   #  ------------------------------------------------------------------------------# # 1: Check the reset state#  ------------------------------------------------------------------------------#         430 ns:  Test passed#   #  ------------------------------------------------------------------------------# # 2: Mode '0' test#  ------------------------------------------------------------------------------#         630 ns:  Walk a '1' across the register data bus#        1290 ns:  Test passed#   #  ------------------------------------------------------------------------------# # 3: Mode '1' test#  ------------------------------------------------------------------------------#        1490 ns:  Walk a '1' across the register data bus#        2150 ns:  Test passed#   #  ==============================================================================#  Simulation complete#  ==============================================================================#  ** Note: stop#     Time: 2350 ns  Iteration: 0  Instance: /example_tb
    In Modelsim, under Linux, I don't think you'll need the {} when you change directories, eg. cd /home/luiz/temp/modelsim_example, should work.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Can i create a testbench with altera maxplus II?

    --- Quote End ---

    No. You create a testbench with a text editor.

    You can manually draw stimulus waveforms in the MAX+PLUS II simulator waveform editor, and then run that simulation.

    I personally prefer to use Modelsim.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    It is good to use this language, But meanwhile show here way to use Verilog, because I want to use this, even I've great command on this language..

    --- Quote End ---

    Verilog is no longer ... its now called SystemVerilog :)

    If you want to see a very simple example of SystemVerilog testbenches, please see this tutorial on the AlteraWiki:

    http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hello all, Mike here. I'm new to the forums. I'm new to learning FPGAs/VHDL. I'm trying to add some new skills. I purchased an ED1 board and a book "Rapid Prototyping of Digital Systems". The book uses Quartus II example but unfortunately doesn't cover the new version 13 of the web edition. This thread is related so I thought I would just continue on with it instead of creating a new one.

    So, I created the simple OR gate design in the block diagram/schematic window shown in the beginning of the book but the book uses the vector waveform file to simulate the design. Obviously they are using the Altera ModelSim software which I have downloaded the starter version of.

    I have no clue how to proceed at this point to simulate this simple design. Can these "schematic capture" designs be simulated in ModelSim?

    Any help would be greatly appreciated!

    Thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi Mike,

    --- Quote Start ---

    I'm new to learning FPGAs/VHDL ... I created the simple OR gate design in the block diagram/schematic window ...

    --- Quote End ---

    Stop right there! Take my advice (and the advice of many others I am sure), start by using VHDL or SystemVerilog (it doesn't matter which, eventually you'll use or at least need to read both).

    Look at the files in the post above, and the tutorial I linked to.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Dave, thanks for the quick reply. I'm glad you said that. I had been debating in my mind whether or not just to grab a book on VHDL and jump in that way. I think you helped me decide.

    Thanks!