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Altera_Forum
Honored Contributor
14 years agoHi Luiz,
What language are you using? VHDL or Verilog? I'll post a simple testbench example to get you started. Cheers, DaveHi Luiz,
What language are you using? VHDL or Verilog? I'll post a simple testbench example to get you started. Cheers, Dave