Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHi Mike,
--- Quote Start --- I'm new to learning FPGAs/VHDL ... I created the simple OR gate design in the block diagram/schematic window ... --- Quote End --- Stop right there! Take my advice (and the advice of many others I am sure), start by using VHDL or SystemVerilog (it doesn't matter which, eventually you'll use or at least need to read both). Look at the files in the post above, and the tutorial I linked to. Cheers, Dave