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Altera_Forum's avatar
Altera_Forum
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15 years ago

Modelsim resimulation after QuartusII synthesis

Hi all,

I created a testbench for a VHDL module, then I simulated it with Modelsim.

Now I have a problem:

I synthesized the module with Quartus II, but now I've to do an after synthesis simulation with Modelsim, so I've to resimulate the module integrating it in the same testbench I used before synthesis.

Can QuartusII get me a sort of "VHDL synthesized file" of my module that I can easily integrate into the old testbench to resimulate it with Modelsim?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Yes, find the module_name.vho files.

    There will several of them, a generic one and one for each timing corner.

    You can setup Quartus to call ModelSim directly, using the Native Link feature.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    - how works the Native Link feature method to recall Modelsim?

    - [...yes, find the module_name.vho files...]

    And where is the? .vho files? I can't find them into the project root.

    However, I'll write here what I've done with my CORE vhdl:

    <functional simulation>

    • I extracted it from testbench

    • I put it into QuartusII like a new project

    • created new waveform vector file

    • functional analysis: start analysis&elaboration

    • create netlist: Processing -> Generate functional simulation netlist

    • start simulation <end functional simulation>

    <timing analysis>

    • Choose analysis method: assignments->timing analysis settings->use classic timing...

    • start compilation

    Is all correct or is something missing?

    Thanks a lot for your answers.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hey Itosone,

    you can start modelsim simulation(native link feature) from quartus from Tools-> Run EDA Simualtion Tool -> EDA RTL Simulation menu. Notice that under Run EDA Simuation Tool menu, there are two sub menus, EDA RTL Simuation is for functional simulation, and EDA Gate Level Simulation is for Timing Simulation.

    The *.vho files can be find in ../simulation/modelsim folder.