ModelSim "out of range" issue

It's a feature of the simulator to detect overflows of range constrained signals. In synthesized logic, integer signals are represented by signed or unsigned bit vectors and will silently wrap around on overflow.

To achieve a consistent simulation in this regard, you need to do this:

- set integer constraints equal to the range of the respective signed or unsigned number (you already did in your code)

- add overflow handling or modulo operations (considering wrap around)

Or assure by design, that no overflow occurs.