ModelSim Newbie

Hello All,

I've just started learning Verilog and as a part of the process i decided to test the testbenches with Verilog PE Student Edition 6.4 .

When i compile a verilog file ,it compiles without any error but i have no object file after that! How can i simulate the code?

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module stimcrct;

reg A,B,C;

wire x,y;

circuit_with_delay cwd(A,B,C,x,y);

initial

begin

A = 1'b0 ; B = 1'b0 ; C = 1'b0;

# 100

A = 1'b1 ; B = 1'b1 ; C = 1'b1;

# 100 $finish;

end

endmodule

module circuit_with_delay (A,B,C,x,y);

input A,B,C;

output x,y;

wire e;

and# (30) g1(e,A,B);

or # (20) g3(x,e,y);

not# (10) g2(y,C);

endmodule

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Please HELP !!!

Best Regards