Forum Discussion
junyoung2
New Contributor
New ContributorModelsim.ini setting
Hello, I learned about a setting called vlog while searching for bit width mismatch. I confirmed that if you set anything in the folder called Modelsim.ini, it will alert you when bit width does not...
KennyT_altera
Super Contributor
Super ContributorThis seems to be same question on https://community.intel.com/t5/Intel-Quartus-Prime-Software/wire-assignment-in-verilog/m-p/1653904#M85097. We shall close this case.
