Altera_Forum
Honored Contributor
9 years ago[ModelSim] How to set design files to be recognized as SystemVerilog also in Modelsi?
Hello,
What settings should I do so that Quartus-II will recognize all the "*.v" files as SystemVerilog files for synthesys as well as for simulations? I did the following settings in the Project Navigator window: 1) RightClick on a file 2) select 'Properties' 3) select 'Type: SystemVerilog HDL File' But, when I invoke ModelSim from Quartus-II, it performs the following commands:
vlog -vlog01compat -work work +incdir+L:/projects/RFGen/amp/rtl/sync {L:/projects/RFGen/amp/rtl/sync/sync_att.v}
vlog -vlog01compat -work work +incdir+L:/projects/common/rstn {L:/projects/common/rstn/rstn_sync.v}
So, the tool does not compile the files as SystemVerilog, but as just Verilog-2001 files (use -vlog01compat switch instead of -sv switch) So, what settings should I do in the Quartus-II so that it will generate the following lines for the simulation (-sv switch will be instead):
vlog -sv -work work +incdir+L:/projects/RFGen/amp/rtl/sync {L:/projects/RFGen/amp/rtl/sync/sync_att.v}
vlog -sv -work work +incdir+L:/projects/common/rstn {L:/projects/common/rstn/rstn_sync.v}
Thank you