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Altera_Forum's avatar
Altera_Forum
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9 years ago

[ModelSim] How to set design files to be recognized as SystemVerilog also in Modelsi?

Hello, What settings should I do so that Quartus-II will recognize all the "*.v" files as SystemVerilog files for synthesys as well as for simulations? I did the following settings in the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Can I recommend you follow the recognised working practice and use the .sv suffix for SystemVerilog files? Then you won't have any of these issues.

Alternatively, don't run ModelSim from within Quartus. Run it up separately and use your own tcl script (perhaps initially crafted with help from Quartus) and run it directly from within ModelSim - either via 'Tools' -> 'Tcl' -> 'Execute macro...' or directly on the command line with "do {script}.tcl"

I'm not aware of any other settings within Quartus to help with this issue.

Cheers,

Alex