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I will initialise d_reg to known value to keep modelsim happy
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Hi,
Original code (before I stripped it down to bare minimum) had a sync reset for d_reg and still exhibited the same behavior. Added initial power on state ("= '0;") and it still did the same thing.
In all three cases (reset, power on state, and the above code) the simulator shows the register output settling to '0' within a few ns of the simulation.
I forgot to mention that the RTL simulation works as expected. Even if I totally stuffed up timing closure I'd still expect the clock to the driven...
Any other ideas?
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Paul
Honored Contributor
