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Altera_Forum's avatar
Altera_Forum
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12 years ago

Modelsim ASE: different results for gate-level simulation of VHDL and Verilog netlist

Hello.

I am trying to simulate simple Quartus II project for Cyclone II with M4K memory block in modelsim (test_mem.zip in attachment).

I am setting VHDL output format for netlist and compiling the project.

Then I am running Modelsim ASE, changing directory to simulation/custom and running the followng sequence of commands: 

vlib workvmap work work
vcom -reportprogress 300 -work work test_mem.vho
vsim -L cycloneii -voptargs=+acc -t ns work.test_mem 
add wave -position end  sim:/test_mem/clk
add wave -position end  sim:/test_mem/address
add wave -position end  sim:/test_mem/leds
force -freeze sim:/test_mem/clk 0 0, 1 {20 ns} -r 40ns
force -freeze sim:/test_mem/address 00000000 0
run 200ns

In the Wave window I can see the following result:

(see attachment modelsim1.jpg)

This is what I expected: after first clk rising edge there is a value 0x01 on data bus (which is stored at memory at address 0x0)

Now I am changing netlist output format to Verilog HDL and recompiling Quartus II project.

Then I am stopping previous simulation and running following sequence of commands in Modelsim: 

vlib workvmap work work
vlog -reportprogress 300 -work work test_mem.vo
vsim -L cycloneii_ver -voptargs=+acc -t ns work.test_mem
add wave -position end  sim:/test_mem/clk
add wave -position end  sim:/test_mem/address
add wave -position end  sim:/test_mem/leds
force -freeze sim:/test_mem/clk 0 0, 1 {20 ns} -r 40ns
force -freeze sim:/test_mem/address 00000000 0
run 200ns

In the Wave window I see different result!

(see attachment modelsim2.jpg)

After first clk rising edge there is a zeros on data bus! ANd value from address 0x0 appears on data bus only after second clk rising edge. (After more experiments I found that this is not additional memory latency. It is only returns zeros only after first rising clk edge).

Is it correct behaviour of Modelsim? Maybe I should set some settings for Verilog simulation? (I tried to set simulator tool from custom to Modelsim in Quartus II. Result is same).

Also attaching directory with two generated netlists for simulation (tm2.zip)

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    maybe you had M4k output registered; it was just you were testing between M4K and output register when simulating with VHDL; -and you were testing at output register Q when simulating with Verilog. that is why one clock cycle was enough in first scenario but two cycles was needed to see the memory content in the second scenario (verilog one; register's Q).i suspect that because different format netlists name their nodes differently. if VHDL called "leds" the node that was directly after M4K, now verilog may call same name "leds" to different point in the system, which may be in front of output register; not the M4K itself.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    It's a bit hard to recall this problem after almost two years. But as far as I can remember, read delay occured in Verilog simulations only on the first cycle. Other reads were identical in VHDL and Verilog. (If the delay is caused by registered output then the one-cycle delay will exist every cycle). Also "leds" is not an M4K port, it's top level design port.

    There are new VHDL and Verilog simulation results attached.

    Also, there are new TCL-commands for ModelSim.

    VHDL: 

    vlib workvmap work workvcom -reportprogress 300 -work work test_mem.vho
vsim -L cycloneii -voptargs=+acc -t ns work.test_mem 
add wave -position end  sim:/test_mem/clk
add wave -position end  sim:/test_mem/address
add wave -position end  sim:/test_mem/leds
force -freeze sim:/test_mem/clk 0 0, 1 {20 ns} -r 40ns
force -freeze sim:/test_mem/address 00000000 0
run 80ns
force -freeze sim:/test_mem/address 00000001 80ns
run 200ns

    Verilog: 

    vlib workvmap work workvlog -reportprogress 300 -work work test_mem.vo
vsim -L cycloneii_ver -voptargs=+acc -t ns work.test_mem
add wave -position end  sim:/test_mem/clk
add wave -position end  sim:/test_mem/address
add wave -position end  sim:/test_mem/leds
force -freeze sim:/test_mem/clk 0 0, 1 {20 ns} -r 40ns
force -freeze sim:/test_mem/address 00000000 0
run 80ns
force -freeze sim:/test_mem/address 00000001 80ns
run 200ns