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Altera_Forum
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12 years ago

Modelsim ASE: different results for gate-level simulation of VHDL and Verilog netlist

Hello. I am trying to simulate simple Quartus II project for Cyclone II with M4K memory block in modelsim (test_mem.zip in attachment). I am setting VHDL output format for netlist and compili...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

It's a bit hard to recall this problem after almost two years. But as far as I can remember, read delay occured in Verilog simulations only on the first cycle. Other reads were identical in VHDL and Verilog. (If the delay is caused by registered output then the one-cycle delay will exist every cycle). Also "leds" is not an M4K port, it's top level design port.

There are new VHDL and Verilog simulation results attached.

Also, there are new TCL-commands for ModelSim.

VHDL: 

vlib workvmap work workvcom -reportprogress 300 -work work test_mem.vho
vsim -L cycloneii -voptargs=+acc -t ns work.test_mem 
add wave -position end  sim:/test_mem/clk
add wave -position end  sim:/test_mem/address
add wave -position end  sim:/test_mem/leds
force -freeze sim:/test_mem/clk 0 0, 1 {20 ns} -r 40ns
force -freeze sim:/test_mem/address 00000000 0
run 80ns
force -freeze sim:/test_mem/address 00000001 80ns
run 200ns

Verilog: 

vlib workvmap work workvlog -reportprogress 300 -work work test_mem.vo
vsim -L cycloneii_ver -voptargs=+acc -t ns work.test_mem
add wave -position end  sim:/test_mem/clk
add wave -position end  sim:/test_mem/address
add wave -position end  sim:/test_mem/leds
force -freeze sim:/test_mem/clk 0 0, 1 {20 ns} -r 40ns
force -freeze sim:/test_mem/address 00000000 0
run 80ns
force -freeze sim:/test_mem/address 00000001 80ns
run 200ns