Modelsim ASE: different results for gate-level simulation of VHDL and Verilog netlist

maybe you had M4k output registered; it was just you were testing between M4K and output register when simulating with VHDL; -and you were testing at output register Q when simulating with Verilog. that is why one clock cycle was enough in first scenario but two cycles was needed to see the memory content in the second scenario (verilog one; register's Q).i suspect that because different format netlists name their nodes differently. if VHDL called "leds" the node that was directly after M4K, now verilog may call same name "leds" to different point in the system, which may be in front of output register; not the M4K itself.