Modelsim-Altera Error VHDL package file

Have you included the package in the list of files to be compiled?

You dont add the full path - you just add:

library <mylib>

use <mylib>.<mypackage>.all;

But using a package of components for VHDL entities is now redundant and can be error prone. For a start, it requires almost identical copies of the entities in the package, which means you need to maintain two bits of code that are bascially the same. If there is a missmatch, you will not notice until elaboration (which can take a while in large synthesis runs). The use of direct instantiation avoids both of these problems because the checks are done at compile time and you dont need to maintain the code twice (ie. you dont need a package of components at all).

direct instantiation is done like this:

my_inst : entity <mylib>.<myent>
generic  map (
)
port map (
);

This is a feature that all synthesis tools support and has been a part of VHDL for more than 20 years (but is hardly ever taught in books unfortunately).

Components are still required if you have an entity that comes from a non VHDL source eg. Verilog, netlist etc.

Yes your right this how i have listed my library :

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY CPU;

USE CPU.cpu_components_pkg.ALL;

It compiles in Quartus without any warning or errors , its only when i do RTL simulation , that Modelsim spits out error about the package library .

All files are in the same folder .

I guess i have to use direct instantiation in my top file to get rid of this error