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Altera_Forum
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10 years ago

Modelsim-Altera Error VHDL package file

Hi , I am working on a VHDL project with many components , i have written a package file with all components declared in it and its been added as a library in my Top file . The project com...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

what errors? did you create the cpu library in modelsim? did you compile the cpu_components_pkg into the cpu library?