Modelsim-Altera Error VHDL package file

Yes your right this how i have listed my library :

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY CPU;

USE CPU.cpu_components_pkg.ALL;

It compiles in Quartus without any warning or errors , its only when i do RTL simulation , that Modelsim spits out error about the package library .

All files are in the same folder .

I guess i have to use direct instantiation in my top file to get rid of this error