ModelSim-Altera Error loading design

Hello,

This is my first time using ModelSim and writing testbenches, so this may sound like a silly problem. But I am having problems simulating my project on ModelSim from Quartus II. Here is the testbench I have written up for the project:

module test_tgen;

reg CLK_IN;

reg reset;

reg IN_4ms;

reg OUT_4ms;

reg OUT_1ms;

reg OUT_20KHZ;

reg LOST_SINK;

timing_gen_block mytiming_gen(reset, IN_4ms, CLK_IN, OUT_4ms, OUT_1ms, OUT_20KHZ, LOST_SINK);

initial // Clock generator

begin

CLK_IN = 0;

forever# 8 CLK_IN = !CLK_IN;

end

initial // Test stimulus

begin

reset = 0;

IN_4ms = 1;# 5 reset = 1;# 250 IN_4ms = 0;

end

initial

$monitor($stime,, reset,, IN_4ms,, CLK_IN);

endmodule

Now this compiles just fine. But when I try to simulate it in ModelSim from Quartus II by selecting tools > run eda simulation tool > eda rtl simulation, I get the following output in ModelSim:

# Reading C:/altera/91/modelsim_ase/tcl/vsim/pref.tcl # do Timing_Gen_block_run_msim_rtl_verilog.do # if {[file exists rtl_work]} {# vdel -lib rtl_work -all# }# vlib rtl_work# vmap work rtl_work# Copying C:\altera\91\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini# Modifying modelsim.ini# ** Warning: Copied C:\altera\91\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.# Updated modelsim.ini.# # vlog -sv -work work +incdir+C:/Users/Travis/ESSM\ FPGA\ Project/FPGA\ Code/Timing_Gen_block {C:/Users/Travis/ESSM FPGA Project/FPGA Code/Timing_Gen_block/Timing_Gen_if.sv}# Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009# -- Compiling module Timing_Gen_if# # Top level modules:# Timing_Gen_if# # vlog -sv -work work +incdir+C:/Users/Travis/ESSM\ FPGA\ Project/FPGA\ Code/Timing_Gen_block {C:/Users/Travis/ESSM FPGA Project/FPGA Code/Timing_Gen_block/test_tgen.sv}# Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009# -- Compiling module test_tgen# # Top level modules:# test_tgen# # vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L stratixiii_ver -L rtl_work -L work -voptargs="+acc" Timing_Gen_block# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L stratixiii_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps Timing_Gen_block # ** Error: (vsim-3170) Could not find 'C:\Users\Travis\ESSM FPGA Project\FPGA Code\Timing_Gen_block\simulation\modelsim\rtl_work.Timing_Gen_block'.# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./Timing_Gen_block_run_msim_rtl_verilog.do PAUSED at line 12

Because of the "Error loading design", my project won't go straight into the simulation . I have the Timing_Gen_block.sv file in the same folder as the others, but am unsure as how to have it recognized. Any suggestions as to what I missed or things I am doing wrong to get the "Error loading design"?

Thanks,

T Miller