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Altera_Forum's avatar
Altera_Forum
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16 years ago

ModelSim-Altera Error loading design

Hello, This is my first time using ModelSim and writing testbenches, so this may sound like a silly problem. But I am having problems simulating my project on ModelSim from Quartus II. Here is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I had the exact same problem recently. I didn't really figure out exactly what has going wrong, but I figured out a way to get past it.

The script seems to be triggering an error on the following statements: 

if {} {
    vdel -lib rtl_work -all
}
There is an error deleting rtl_work becusae it cannot be found. I have no idea how this can happen as the if statement should be checking for this case.

To get past this, I simply loaded the script (Timing_Gen_block_run_msim_rtl_verilog.do in your case) into an editor. I then copied everything past the above lines I mentioned and pasted them into the Modelsim transcript window. The simulation then ran as normal. The next time I started the simulation from Quartus, the problem did not repeat itself.