ModelSim (Altera) & TCL Problems

--- Quote Start ---

I'm having problems with the TCL commands in ModelSim SE - Altera Version.

(I'm running ModelSim ALTERA STARTER EDITION 10.0c)

--- Quote End ---

Modelsim-ASE does not support Tk.

Cheers,

Dave

Ah, okay. I was starting to come to that conclusion, but none of the documentation mentioned this. Thanks Dave.

I'm curious if there is a way to enumerate all of the signals that are currently in the Wave window just using TCL?

As a real kludge I think I can save the wave format using the following:

write format wave -window .main_pane.wave.interior.cs.body.pw.wf {C:/wave.do}

Then I can parse the output to find all the signals, but I would hope there is an easier way...?

(I'm trying to put together a generic TCL script which will find all of the signals I've manually added to the wave window, add those to a list then export it to a tabular file, for use in Python.)

--- Quote Start ---

I'm trying to put together a generic TCL script which will find all of the signals I've manually added to the wave window, add those to a list then export it to a tabular file, for use in Python.

--- Quote End ---

Why bother? Since you're using it to populate the wave window, why can't you just have the python use the .do file directly.

For example, when I use Modelsim, I just create a Tcl procedure with the same name as the testbench, and inside that procedure call vsim and populate the wave window using the .do file.

Cheers,

Dave

Sorry, I should be a little more clear on my intent. I'm trying to export all the wave signal's simulated data, not just the list of signals names to Python.

The only way I've found to do this is to first export the wave data to the List window, then Export it as Tabular data.

So, I'm trying to put together a generic TCL script that will automatically export whatever simulated data is in my Wave window to a file for import in Python.

Seemingly I have to push all the data to the List window first, then I can export it. (Perhaps there is a better way?)

--- Quote Start ---

Perhaps there is a better way?

--- Quote End ---

What is the "Big Picture" here? Why do you want the data in Python?

You could format the data directly in SystemVerilog or VHDL and write the data files in exactly the format you want. The HDL languages are just as capable as any other programming language.

For example, I'll sometimes have the testbench write a MATLAB script, and then I can generate plots without having to actually write MATLAB code :)

Cheers,

Dave

No "Big Picture" yet, at this point I'm just trying to see what kind of connectivity is possible between different tools. :-)

TBH, I'm much more familiar with Python (& Matplotlib) than I am with TCL and SystemVerilog. I've seen some recommended methods for using VHDL constructs to automatically write their simulated data out to a file, from what I've seen you have to add a construct for each signal you want to probe. This would probably be best for "proper" design flows, but maybe a little in-flexible for a hobbyist poking around :-)

--- Quote Start ---

No "Big Picture" yet, at this point I'm just trying to see what kind of connectivity is possible between different tools. :-)

--- Quote End ---

Fair enough.

--- Quote Start ---

TBH, I'm much more familiar with Python (& Matplotlib) than I am with TCL and SystemVerilog. I've seen some recommended methods for using VHDL constructs to automatically write their simulated data out to a file, from what I've seen you have to add a construct for each signal you want to probe. This would probably be best for "proper" design flows, but maybe a little in-flexible for a hobbyist poking around :-)

--- Quote End ---

Well, in my experience, I don't care what the waveforms look like after the testbench has been run in the simulator and all tests have passed. Sure, I'll create figures for sections of waveforms to show that the interface implements the timing 'per the datasheet' of whatever I'm interfacing to. However, there's very little need for manipulating the waveforms after-the-fact.

So, although you're having fun playing with Python, perhaps the time would be better spent playing with SystemVerilog, VHDL, or Tcl. I mean, hey, they're just languages, and once you've learned a dozen or so, they all blend together ... :)

Cheers,

Dave

If ModelSim-ASE supported Tk I might be more interested in learning Tcl, but w/o Tk, Python appears to be the superior alternative.

At my job I spend my day verifying hardware (mixed signal ASICs), and I typically use Python to extract and process data from the hardware, Scopes and other test equipment....hence my preference to move data over to Python :)

I'll look into writing a Tcl script to parse the wave.do file as I mentioned above, I'll drop back once I get it figured out.

Thanks for the advice Dave.

Regards,

Chris

--- Quote Start ---

At my job I spend my day verifying hardware (mixed signal ASICs), and I typically use Python to extract and process data from the hardware, Scopes and other test equipment....hence my preference to move data over to Python :)

--- Quote End ---

Yeah, I understand :)

--- Quote Start ---

I'll look into writing a Tcl script to parse the wave.do file as I mentioned above, I'll drop back once I get it figured out.

--- Quote End ---

I still think you'd be better off generating the file directly from an HDL language ...

Note that Modelsim-SE does support Tcl/Tk, so if you have that at work, you can always play with Tcl/Tk in that version of Modelsim.

Cheers,

Dave

Okay, maybe you're right, if I'm manually adding signals to the wave window and just playing around, it only takes 5 seconds to drag drop and export the data. The time it takes me to learn enough Tcl to put together a kludge to parse the file would probably surpass the time I spend manually exporting the data. Learning to push the data out via SystemVerilog would pay dividends in the long run.

Most of our design guys use Eldo, but maybe there is an available Modelsim-SE seat floating around somewhere that I could play with, good idea.