Honored Contributor
Honored ContributorNo "Big Picture" yet, at this point I'm just trying to see what kind of connectivity is possible between different tools. :-)
TBH, I'm much more familiar with Python (& Matplotlib) than I am with TCL and SystemVerilog. I've seen some recommended methods for using VHDL constructs to automatically write their simulated data out to a file, from what I've seen you have to add a construct for each signal you want to probe. This would probably be best for "proper" design flows, but maybe a little in-flexible for a hobbyist poking around :-)
