Modelsim - VHDL common question.

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the design is only using memory blocks, take a look at the Total memory bits used in your report

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Thanks thepancake very much. I thought it had logic gate because i have some code to read the memory.

Do you know about altrom?

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you specified unregistered outputs in the instantiation of the ROM, but then inferred output registers in the code, so i imagine the output registers were packed into the block RAM

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Thank you.

Dear my friends

When i simulate VHDL code by Modelsim, I got some warning about arithmetic

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# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

# Time: 1020 ns Iteration: 1 Instance: /testbench_svpwm/u/state

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

# Time: 1020 ns Iteration: 1 Instance: /testbench_svpwm/u/state

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

# Time: 1260 ns Iteration: 1 Instance: /testbench_svpwm/u/state

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

# Time: 1260 ns Iteration: 1 Instance: /testbench_svpwm/u/state

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).

# Time: 1380 ns Iteration: 1 Instance: /testbench_svpwm/u/state

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And when I run step by step my code, I saw, when this code was executed, the warning display. I don't know why this this warning display. Could you help me?

This is my declare

use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
signal TAA,TBB          : STD_LOGIC_VECTOR(11 downto 0):=(others =>'0');
signal TAM				: STD_LOGIC_VECTOR(11 downto 0):=(others =>'0');
signal TAO,TBO,TCO		: STD_LOGIC_VECTOR(11 downto 0):=(others =>'0');

and this code has warning when i run it by modelsim

elsif CNT=x"08" then
	TAM  <= x"410" -TAA -TBB;    
elsif CNT=x"09" then
	TAO  <= '0' & TAM(11 downto 1);  
elsif CNT=x"0A" then
	TBO  <= TAO + TAA;
elsif CNT=x"0B" then
	TCO  <= TBO + TBB; ;

Thank you very much.

Happy new year to all my best friend

hi

I need a simple calculator with -,+,/,* operation & logic operation & shift right & shift left that I enter digits from keyboard and show them on lcd.So I must have keyboard component and lcd component for digits (VHDL). can u help me? I've found calculator codes from this site but that doesnt have logic and shift operations. please help me. I cant find component lcd and keyboard from internet. Can you give me codes of this calculator that I want? please help me. thanks a lot