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Altera_Forum
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15 years ago

Modelsim - VHDL common question.

Dear all my friend I make this thread to post the question related to Modelsim and VHDL I hope everybody can help me answer. Thank you very much. Best regards.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Your warning are most likely due to the default state of signals (like the CNT signal earlier in this post) beginning the simulation as 'X' or 'U', since you have no reset circuitry.