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Altera_Forum
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15 years ago

Modelsim - VHDL common question.

Dear all my friend I make this thread to post the question related to Modelsim and VHDL I hope everybody can help me answer. Thank you very much. Best regards.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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the design is only using memory blocks, take a look at the Total memory bits used in your report

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Thanks thepancake very much. I thought it had logic gate because i have some code to read the memory.

Do you know about altrom?