Mixed TDF/VHDL/BDF Project Files

I believe it depend the IPs that you are using. For example, in QII 15.0, some of the IP ie transceiver PHYs is generated in Qsys as compared to the .v/vhd file in QII 13.1.

You shouldn't need to convert anything. Quartus can compile projects containing all 3 sources.

Yes, you are lucky one )

I am not sure about your question for migrating to another chip, never had to do it across any different families. Certainly pin assignments and timing constraints are important.

try to add ouptputs through assignment editor.

Ok, understand about the migration question you posted, but wondering about the Modelsim question with running Navlink on project. Why doesn't it automatically open the project files when Modelsim opens from tools>Run Simulation Tools>Run Gate Level or Run RTL. In previous executions it has opened the project for simulation. Do I have to create the project again even though it has been previously created?

...I recently updated to 15.1 lite -> something prevent full launch of Modelsim from Quartus shell, the processes {vsim vish vlm} start but no any visible window.

What I meant was recreating the project in Modelsim, not Quartus. If Navlink was really coupled to Modelsim, I would think it should automatically bring in the .vho or other files necessary to run simulation. But, it doesn't and it seems the library files under the "work" directory are incomplete or not there. This has worked before in Quartus 13.0, but not 14.0 or 15.0. It use to bring up a jump start project window. Has this changed in the newer Modelsim?

I am not sure but *.vht (testbench file) generated through quartus could be opened with Modelsim.

I searched in all modelsim directories for any *.vht files, but didn't find anything. I thought if Navigator is set up right, it should generate a test bench .vhdl or .vo. As mentioned previously I have never had to worry about this before with Quartus 13.0.