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Honored Contributor
Honored ContributorMixed TDF/VHDL/BDF Project Files
When using mixed HDL files in a project, I presume that as long as you converter all AHDL (.tdf) files to vhdl and include them in the project list that is okay. This would included schematic (bdf) f...
Altera_ForumHonored Contributor
Honored ContributorI am not sure about your question for migrating to another chip, never had to do it across any different families. Certainly pin assignments and timing constraints are important.
I do have another question about Modelsim, but don't know if this is the right forum. It seems that using Tools>Run RTL Simulation>RTL Simulation does not automatically open project in Modelsim with object list from "work" directory. This has occurred in with other project if successfully compiled.
