Mixed TDF/VHDL/BDF Project Files

I am not sure about your question for migrating to another chip, never had to do it across any different families. Certainly pin assignments and timing constraints are important.

I do have another question about Modelsim, but don't know if this is the right forum. It seems that using Tools>Run RTL Simulation>RTL Simulation does not automatically open project in Modelsim with object list from "work" directory. This has occurred in with other project if successfully compiled.