mixed HDL simulation model

I have a design in multi HDL languages. I use Quartus 13.0 wnd my target device is Cyclone V

When I generate a build with QSYS, it generates Verilog and VHDL files for different IPs in synthesize folder.

I try to make simulation model. For now everything is VHDL except a_block. I selected option VHDL for “create simulation model” in generation tab of QSYS and I see this error for a_block IP in QSYS:

Error: a_block: a_block does not support generation for VHDL Simulation. Generation is available for: Quartus Synthesis, Verilog Simulation.

I did a little bit of research and found that there is a setting to generate simulation model in VHDL. I added this setting in tcl of a_block IP:

set_module_property simulationModelInVHDL “true”

I got the same error! any idea on this?