Mixed blocking and non- with always@ ?

FPGA technologies are roughly the same, but the code the accept is different. Then you have Asic technologies that are different again (there are similarities, but again differences too).

Afaik, VHDL (and likely verilog) was not originally meant as a synthesisable language. It was originially intended to model digital circuits (VHDL standardised in 1987, Verilog 1995). Then vendors started to support the languages for synthesis.

Rather than trying to understand the language, it is much better to understand the technology first. Then from there, you understand how to build the circuits with HDL, then over time you'll probably learn how the language works.