Metastability avoidance...again!

--- Quote Start ---

Hi folks,

I have an ADC which provides LVDS data to the FPGA (cyclone 3). The data clock is fed to a dedicated LVDS mega-function, as is the serial data. I have a frame clock that also comes from the ADC to the FPGA, the frame clock is used to latch the data into registers. The data leaving the LVDS mega-function is therefore synchronous to the ADC data clock only. This implies that I will need to synchronize the de-serialized data to the sysclk (400MHz) along with the frame clock to ensure I avoid meta-stability between the ADC clock domain and the sysclk domain.

Is this correct, I only ask because the de-serialized data is 4 channels of 10 bit data (40bit in total), and to sync in the normal way by using 3 stage FFs clocked by sysclk is going to cost me some serious logic space in a cyclone 3.

AM i on the right track? Thanks in advance...

D

--- Quote End ---

you need to follow the general clock crossing rules, which I believe are as follows.

1) If your clocks are same frequency, synchronised, in phase: resync is never needed.

2) If your clocks are same frequency, synchronised, not in phase: resync is not needed but could help failed timing.

3) If your clocks are not same frequency but synchronised and related by a fixed pattern: resync is not needed but could help failed timing.

4) If your clocks are same or not same frequency but not synchronised: resync is definitely needed.

There are two issues here, timing and bridging samples across. (A dc fifo does it all)

Hi again,

I did just read something about not using 3 stage syncs for parallel data and have come to the conclusion that DSL has just mentioned.

I can tell you a little more, and should've mentioned in my first post. The ADC recieves its clock from the FPGA in the first place. I have a PLL generating a 40MHz clock which is sent as a single ended signal to the ADC. The ADC then generates the LVDS streams, Data Clock (DDR) and frame clock all of which are differential and are fed back to the CYclone III FPGA on its diffio in banks 5 and 6. This is then fed into the LVDS mega-function (except the frame clock) which de-serializes the data according to the data clock, and the frame clock is used simply to make sure I get the word boundaries correct when reading the values. The logic that then requires this data and frame clock is being clocked at 400MHz from the same PLL.

This suggests to me that this would meet 3) in the list Kaz provided. Because the clocks are not the same freq but are related (phase and skew may have occured). Does that sound about right?

IF so would this be a suitable solution:?

I latch the de-serialized data into a register using the un-syncd frame clock (which is in sync with the adc data clock), The un-syncd frame clock is also fed to a 3 stage sync which will inevitably delay it by 2-3 sysclks (400MHz), I then latch the data from the first register into a second register but on the syncd frame clock? As the sysclock is 10times faster than the frame clock, all this should occur before the next frame is presented from the ADC... does this sound reasonable? Or have I missed something else?

Thanks for all your advice btw, all this metastability stuff is new to me and sometimes the info out on that there web can be as confusing as it is enlightening!

D