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Hi folks,
I have an ADC which provides LVDS data to the FPGA (cyclone 3). The data clock is fed to a dedicated LVDS mega-function, as is the serial data. I have a frame clock that also comes from the ADC to the FPGA, the frame clock is used to latch the data into registers. The data leaving the LVDS mega-function is therefore synchronous to the ADC data clock only. This implies that I will need to synchronize the de-serialized data to the sysclk (400MHz) along with the frame clock to ensure I avoid meta-stability between the ADC clock domain and the sysclk domain.
Is this correct, I only ask because the de-serialized data is 4 channels of 10 bit data (40bit in total), and to sync in the normal way by using 3 stage FFs clocked by sysclk is going to cost me some serious logic space in a cyclone 3.
AM i on the right track? Thanks in advance...
D
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you need to follow the general clock crossing rules, which I believe are as follows.
1) If your clocks are same frequency, synchronised, in phase: resync is never needed.
2) If your clocks are same frequency, synchronised, not in phase: resync is not needed but could help failed timing.
3) If your clocks are not same frequency but synchronised and related by a fixed pattern: resync is not needed but could help failed timing.
4) If your clocks are same or not same frequency but not synchronised: resync is definitely needed.
There are two issues here, timing and bridging samples across. (A dc fifo does it all)
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