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Altera_Forum
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11 years ago

Metastability avoidance...again!

Hi folks, I have an ADC which provides LVDS data to the FPGA (cyclone 3). The data clock is fed to a dedicated LVDS mega-function, as is the serial data. I have a frame clock that also comes fro...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Also you can't use separate 3 stage synchronisers for parallel data - you end up with bits from two different source 'words'.