MegaWizard 2x8k Dual Port Memory

Try to Convert a Project to Cyclone III but need Help with the Memory Type

module vidram(
                     output 	data_out,	// cpu interface		     input     	data_in,
		     input    cpu_addr,
		     input          	we,
                     output 	video_data,	// video hardware intf
                     input 	video_addr,
		     input          	clk
	     );
    // A single Spartan 8x2k 2-port RAM.  Easy.
    RAMB16_S9_S9
	ram(.DIA(data_in),
            .DIPA(1'b0),
	    .DOA(data_out),
            .DOPA(),
	    .ADDRA(cpu_addr),
	    .WEA(we),
	    .ENA(1'b1),
	    .SSRA(1'b0),
	    .CLKA(~clk),	// see description
            .DIB(8'h00),
            .DIPB(1'b0),
            .DOB(video_data),
            .DOPB(),
            .ADDRB(video_addr),
            .WEB(1'b0),
            .ENB(1'b1),
            .SSRB(1'b0),
            .CLKB(~clk)		// see description
    );
         
endmodule // vidram

module vidram (	clock,
	data,
	rdaddress,
	wraddress,
	wren,
	q);
	input	  clock;
	input	  data;
	input	  rdaddress;
	input	  wraddress;
	input	  wren;
	output	  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1	  clock;
	tri0	  wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
	wire  sub_wire0;
	wire  q = sub_wire0;
	altsyncram	altsyncram_component (
				.address_a (wraddress),
				.clock0 (clock),
				.data_a (data),
				.wren_a (wren),
				.address_b (rdaddress),
				.q_b (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken0 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_b ({8{1'b1}}),
				.eccstatus (),
				.q_a (),
				.rden_a (1'b1),
				.rden_b (1'b1),
				.wren_b (1'b0));
	defparam
		altsyncram_component.address_aclr_b = "NONE",
		altsyncram_component.address_reg_b = "CLOCK0",
		altsyncram_component.clock_enable_input_a = "BYPASS",
		altsyncram_component.clock_enable_input_b = "BYPASS",
		altsyncram_component.clock_enable_output_b = "BYPASS",
		altsyncram_component.intended_device_family = "Cyclone III",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 2048,
		altsyncram_component.numwords_b = 2048,
		altsyncram_component.operation_mode = "DUAL_PORT",
		altsyncram_component.outdata_aclr_b = "NONE",
		altsyncram_component.outdata_reg_b = "CLOCK0",
		altsyncram_component.power_up_uninitialized = "FALSE",
		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
		altsyncram_component.widthad_a = 11,
		altsyncram_component.widthad_b = 11,
		altsyncram_component.width_a = 8,
		altsyncram_component.width_b = 8,
		altsyncram_component.width_byteena_a = 1;
endmodule