Altera_ForumHonored Contributor9 years agoMegaWizard 2x8k Dual Port Memory Try to Convert a Project to Cyclone III but need Help with the Memory Type Orginal Code module vidram( output data_out, // cpu interface input data_in, ...Show More
Altera_ForumHonored Contributor9 years ago --- Quote Start --- will not work --- Quote End --- No, why don't you copy the original port assignment, e.g. disable wren_b?
Recent DiscussionsFree Licence for Max+PlusIIMAX10 ADC - getting it to simulate in ModelsimFailed to run ip-setup-simulation:Compile option not saved (reversed to default)How to fix Error(23782): Failed to find an expected report